Modern dynamic random access memory (DRAM) devices are typically fabricated using a process that does not allow for efficient high speed input/output (I/O) of data. Similarly, the process used to fabricate a high speed I/O device typically is not optimized for producing a DRAM device. Manufacturers of DRAM devices are finding it increasingly difficult to develop and fabricate an I/O interface that is compatible with emerging DRAM interface standards, such as DDR4 (double data rate version 4), and newer DRAM interface standards, using DRAM fabrication techniques.
Therefore, it would be desirable to have a way of interfacing a modern DRAM device to a modern high speed I/O interface while maximizing both technologies.